Flexibilis Ethernet Switch

Flexibilis LogoFlexibilis Ethernet Switch (FES) is a triple-speed (10Mbps/100Mbps/1Gbps) Ethernet Layer-2 switch IP core compatible with IEEE 802.1D. FES is suitable for applications such as:

  • Wireless Backhaul
  • Wireline Access
  • Data Center Bridging

FES compatibility has been tested in three ISPCS plug-fests.

Multi-Gigabit Forwarding Engine

The core of FES is a multi-gigabit forwarding engine capable of serving up to eight full-duplex gigabit Ethernet ports, thus forwarding eight gigabits of data every second. All the ports have four priority queues enabling four different priority levels. At congestion situation frames are discarded in WRED (Weighted Random Early Detection) fashion, which drops frames from low priority queues first, preserving the more important streams also during congestion. Using Store-and-Forward technique enables error-checking of the frames and eliminates the possibility of the switch forwarding broken frames, which is impossible for Cut-through type of switches. Forwarding latency is minimal, thanks to gigabit operation.

To preserve valuable FPGA internal memory resources the switch core includes advanced memory management functionality: frames are stored in centralized manner and in fragments of 512 bytes. This prevents small frames from consuming the same amount of memory as maximum sized frames. Also by not having fixed size per port queues prevents the currently empty queues from allocating memory that could be used by the other queues. 512 kbits of FPGA internal memory is reserved for output queues, which makes it possible to queue 42 to 128 Ethernet frames depending on their length.

Built-in Precision Time Protocol Support

Precision Time Protocol (PTP), defined in IEEE standard 1588, enables precise synchronization of device clocks in packet based networks. Devices are automatically synchronized to the most accurate clock in the network. The protocol supports system wide synchronization accuracy usually in sub microsecond range with minimal network and local clock computing resources. The protocol is used in applications such as test and measurement, power-line management, industrial automation and telecom applications.

PTP accuracy is based on an assumption that the delay in Ethernet is approximately constant and symmetric. Ethernet switches cause fluctuation to the packet delay, thus decreasing PTP synchronization accuracy. Transparent PTP switch functionality removes these problems and enables precise synchronization of clocks in switched Ethernet. When using Gigabit fiber Ethernet FES is able to achieve nanosecond class accuracy in clock transfer.

Optional Host CPU

The optional host CPU can be used to manage the functionality of FES or to implement Spanning Tree Protocol (STP) or Rapid Spanning Tree Protocol (RSTP). FES supports MDIO interface for host CPU access to FES register and the registers of the PHY chips connected to FES. The CPU port can be configured as a management port which enables the CPU to be able to send and receive any kinds of Ethernet frames to/from any other port. FES can also be used without a host CPU, the IP core can automatically poll the status of the connected PHY interface chips and adjust its interface speed accordingly.

For pricing or additional technical information, please contact Flexibilis Oy by visiting www.flexibilis.com.


  • Ethernet Layer-2 switch
  • Compatible with IEEE standard 802.1D “Media Access Control (MAC) Bridges”
  • Wire-speed packet forwarding
  • Non-blocking operation
  • Reliable Store-and-Forward operation with data integrity checking
  • Ethernet packet filtering and prioritization
  • 4 priority queues for each port
  • Weighted Random Early Detection (WRED) queue management
  • 512 kbit internal memory for output queues
  • Efficient internal memory management
  • 2048 address MAC-table
  • Automatic address learning and aging
  • Time and frequency synchronization using IEEE1588-2008 Precision Time Protocol v2
  • End-to-end transparent switch functionality
  • Management Ethernet port
  • Triple-speed (10Mbps/100Mbps/1Gbps), full-duplex operation on all ports
  • All of the ports of FES-HSR can be either copper or fiber Ethernet interfaces, or connected to other FPGA blocks
  • Interface options - MII, GMII, RMII and RGMII
  • Automatic polling of connected Ethernet PHY interface chips
  • Rapid Spanning Tree Protocol (RSTP) implementation supported through optional host CPU

Jump to

Block Diagram

FES is available in three different Ethernet interface configurations:

FPGA resource usage varies from about 14,500 FPGA registers (3-port) to about 38,000 FPGA registers (8-port).

Ordering Information

This IP core is supported and sold by Flexibilis, contact Flexibilis at contact@flexibilis.com or visit their website at www.flexibilis.com for more information.


Information Resources
Flexibilis Ethernet Switch IP Core Product Brief
1.0 6/9/2011 PDF 763.8 KB

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