Radiant Version History


Radiant 1.1

  • iCE40 UltraPlus device enhancements and bug fixes
    • New HDL attribute RGB_TO_GPIO.
    • Four new iCE40 UltraPlus bitstream strategy options have been added:
      • Enable Warm Boot
      • Set All Unused IO No Pullup
      • Set NVCM Security
      • SPI Flash Low Power Mode
  • Enhanced Intellectual Property (IP) tools and flow
  • Constraints Syntax and Flow updates
    • Timing Constraints: Added Object Access Command (-of_objects) support which allows flexible and efficient object accesses. Note that this option is supported in constraint files only in Radiant software 1.1. Graphical User Interface support for this option is expected in Radiant 1.2.
    • Physical Constraints: Added -region option support in ldc_prohibit constraint. This option is also supported in ldc_set_location.
    • Timing Constraint Editor:
      • Added set_load constraint
      • Added Disable/Enable checkbox that allows you to easily disable or enable constraints.
  • Tool and Other Enhancements
    • Cross-probe timing path from timing reports. Map and PAR timing reports now have hyperlinks that allow users to view timing paths in Netlist Analyzer, Physical View, and Floorplan View.
    • Detachable Tool Windows. Detach and attach functionality has been added for all tools and views, allowing user to work on a tool outside of the Radiant software environment.
    • Lattice Synthesis Engine (LSE). LSE has significant performance improvements from Radiant software 1.0 including:
      • Improvements in embedded block RAM (EBR), finite state machine (FSM), and digital signal processor (DSP) extraction.
      • Improvements in Area implementation and run time.
    • Power Estimator. A new stand-alone Power Estimator has been added.
    • Simulation Wizard. The Simulation Wizard has been updated to support post-synthesis simulation.
    • Source Template. A new Source Template tab has been added to make it easier to access various templates without the need to have the Source Editor running. The selection of templates has been enhanced. Available templates, in both VHDL and Verilog, include:
      • Common Templates
      • PMI Templates
      • Primitive Templates
      • Attribute Templates
      • Encryption Templates
      • Timing Constraints
      • Physical Constraints
    • Ubuntu operating system. Support for Ubuntu operating system LTS 16.4 has been added

Radiant 1.0 SP1

  • Re-compile with this service pack if users uses the LVDSE IO type in their design.
  • If CCU2 primitives are indicated in the Area Report of the LSE synthesis report file, there is a chance of getting an incorrect synthesis result from carry chain optimizations. It is advised to re-compile the design using this service pack to avoid a simulation and/or hardware operation failure. This fix is applicable for LSE only.
  • Fixed several other key customer defects resolving instability relating to map, place and route in the timing engine.

Radiant 1.0

  • Standardized Timing and Physical Constraints utilizing the popular SDC format to help you easily apply constraints to your designs.
  • Unified Static Timing Analysis from Synthesis to Place & Route to accelerate design timing closure.
  • Enhanced IP Security Flow and Ecosystem to allow efficient distribution of Soft IP’s and to improve 3rd Party Soft IP security.
  • New and Simplified GUI design with option of light or dark color theme.
  • Simplified and Efficient Design Flows and Tools to improve Ease-of-Use.
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