Lattice Blog

Power Management 2.0

Power Management 2.0

Posted 08/01/2017 by Shyam Chandra

In this 6 part series we are looking at the challenges of implementing an efficient power management architecture in today’s complex circuit board designs.

Read more...
Power Management using a Control PLD with on-chip ADC

Power Management using a Control PLD with on-chip ADC

Posted 05/09/2017 by Shyam Chandra

In our 5th post, we will look at one final attempt to develop an efficient power management solution for a modern circuit board. In this model we have come full circle. The control PLD is back in charge of all power management functions.

Read more...
Power Management through PMBus and Control PLD

Power Management through PMBus and Control PLD

Posted 02/14/2017 by Shyam Chandra

Our previous post covered a hybrid architecture, where the control PLD was splitting the power management responsibilities with a dedicated power manager IC. This next option is used by some designs to replace the dedicated power manager IC with a software driven MCU.

Read more...
Power Management Using a Power Manager IC and Control PLD

Power Management Using a Power Manager IC and Control PLD

Posted 11/08/2016 by Shyam Chandra

In our last post, we looked at an architecture where the control PLD controlled all of the power management functionality and identified any weaknesses around congestion and crosstalk. Today, we will review a hybrid architecture that attempts to solve the congestion/crosstalk problems by ...

Read more...
Power Management with a Control PLD

Power Management with a Control PLD

Posted 08/17/2016 by Shyam Chandra

In this 6-part series, we are looking at the challenges of implementing an efficient power management architecture in today’s complex circuit board designs.

Read more...
The Quest for the Optimal Power Management Architecture

The Quest for the Optimal Power Management Architecture

Posted 07/19/2016 by Shyam Chandra

The consumer’s desire for new technology is insatiable. To meet this demand, engineers are constantly striving to make things smaller, faster, cheaper, and better. As sizes shrink and complexity increases, we often find that techniques that have served us well for a long time no longer meet our needs. We must evolve alongside our designs.

Read more...
Simplify board design and debug with Control PLDs

Simplify board design and debug with Control PLDs

Posted 05/10/2016 by Shyam Chandra

Today’s designers face a major challenge: How do I pack more functionality into a board, and do it faster and cheaper? The go-to approach to solving this problem is to implement data path or payload functions using highly integrated ASICs and SoCs. However, the design is not complete by simply connecting all the large devices together.

Read more...
Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.