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Single Wire Aggregation – The FPGA Advantage

Single Wire Aggregation – The FPGA Advantage
Posted 09/09/2020 by Hussein Osman

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For a variety of reasons, a large proportion of today’s electronic systems involve two or more circuit boards or modules. Partitioning the design across multiple boards allows disparate circuit functions to be implemented on different boards, thereby providing a path for incremental system upgrades in the future. Also, multiple boards can be packed into a 3D enclosure with a smaller 2D footprint.

A perennial problem for designers is connecting these boards together in order to transfer data between them. A very common solution is to mount multi-pin connectors on the boards and to use multi-wire harnesses or flex to link the boards together.

Traditional connectors are costly, consume space, and degrade the reliability of the system.
Traditional connectors are costly, consume space, and degrade the reliability of the system.

Unfortunately, each connector pin is a potential point of failure. In addition to adding cost and consuming space, connectors are often the overwhelming factor regarding the reliability -- or lack thereof -- in an electronic system. Contra wise, minimizing the number of inter-board connections reduces cost, reduces space, and increases the reliability of the system.

Fortunately, many of these inter-board signals typically provide only relatively low-speed communications using general-purpose input/outputs (GPIOs) or serial interfaces like I2C (inter-integrated circuit) and I2S (integrated inter-IC sound bus).

These relatively low-speed communications lend themselves to a concept known as single wire aggregation (SWA), in which multiple signals are aggregated into a time division multiplexed (TDM) signal that requires only a single inter-board wire.

One way to implement SWA would be to create a custom application-specific integrated circuit (ASIC) for each product. But there are multiple disadvantages to this approach, not least the high cost and long development times. Even worse, any algorithms and functions implemented in ASICs are effectively “frozen in silicon.” As a result, ASIC-based solutions cannot adapt to changing requirements, such as the head of sales unexpectedly announcing: “The good news is we just accepted a huge order; the bad news is that the customer says we need to replace one of the I2S interfaces with two I2C channels – how soon can we have this available?”

SWA – The FPGA Advantage

Field-programmable gate arrays (FPGAs) provide an ideal solution for implementing SWA because they are extremely flexible and can be quickly and easily customized to implement the required numbers and types of the various communications channels.

For example, tiny, high-performance, ultra-low-power iCE40 UltraPlus™ FPGAs from Lattice Semiconductor can be employed to implement SWA using various combinations of GPIO, I2C, and I2S up to a total of seven channels.

Tiny, high-performance, ultra-low-power iCE40 UltraPlus FPGAs are ideal for SWA applications.
Tiny, high-performance, ultra-low-power iCE40 UltraPlus FPGAs are ideal for SWA applications.

In addition to featuring an ultra-low-power advanced process with static current as low as 75 uA and as little as 1 to 10 mA active current for most applications, iCE40 UltraPlus FPGAs are also available in multiple package options to fit wide range of applications needs, from an ultra-small 2.15 x 2.50 mm WLCSP package optimized for consumer and IoT devices to a 0.5 mm pitch 7 x 7 mm QFN for cost-optimized applications.

Of particular interest is the fact that the iCE40 UltraPlus FPGA’s configuration bitstream can be loaded directly into SRAM-based configuration cells during the prototyping stage of the design. When the iCE40 UltraPlus FPGA is deployed in a product, the configuration can continue to be loaded into the SRAM cells via a microcontroller or external SPI flash memory device if required. Alternatively, iCE40 UltraPlus FPGAs also contain a one-time programmable (OTP) on-chip non-volatile configuration memory (NVCM), which is best suited for mass production. Once the NVCM has been programmed, the device will automatically, quickly, and securely boot from this configuration.

But Who is to Implement the FPGA-based SWA Design?

If the team developing the product already has access to an FPGA designer, then Lattice can provide free access to the Lattice Radiant® design tool, the source code for an easily modifiable parameterized SWA reference design ready to run on the Radiant design tool, an associated Reference Design User Guide, and a SWA demonstration and development board.

But what about those teams that don’t have access to FPGA design expertise? Fear not, because Lattice has you covered. Lattice has created a suite of five pre-synthesized bitstreams providing SWA configurations that address the requirements of a wide range of system designs. A Bitstream User Guide is available from Lattice’s SWA webpage that describes how anyone – including non-FPGA designers -- can quickly and easily load one of these preconfigured SWA bitstreams into an iCE40 UltraPlus FPGA.

Pre-compiled bitstreams are available for five popular SWA configurations.
Pre-compiled bitstreams are available for five popular SWA configurations.

But wait, there’s more, because Lattice also offers a free SWA design service. If you visit Lattice’s SWA development board webpage, you can use an interactive form to specify the unique combination of channels you require for your design, and the Lattice design team will email the corresponding bitstream file to you, typically in less than one business day.

The end result is that every design team can now take full advantage of FPGA-based SWA to connect the multiple circuit boards comprising their design, even if they have no FPGA expertise. All that remains is for me to wish you a happy SWA design experience.

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