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When Less is More: How Signal Aggregation Can Simplify Your Design

When Less is More: How Signal Aggregation Can Simplify Your Design
Posted 02/28/2017 by Abdullah Raouf

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It’s tough being a mobile designer. Whenever new and exciting functionalities are identified, it is up to them to figure out how to implement those new elements into an already “crowded” design. Take a smartphone and new always-on monitoring functionality, for example. Every sensor the designer adds to support always-on monitoring and context awareness must continuously send data to the applications processor (AP). Given the proliferation of interface standards today, the designer of your next smartphone may have to designate two signal paths for I2C or I3C, up to four for SPI, and as many as 20 signal paths for a MIPI D-PHY CSI-2 camera. So it’s not a stretch to say that a single phone could easily end up with up to 40 signals coming from various sensors to the AP.

To make matters worse, the Printed Circuit Board (PCB) in today’s smartphones is typically split across two pieces – one on each side of the battery. Often, designers use a flex PCB to link the two rigid PCBs at low cost. Unfortunately, the flex PCBs are not exactly known for their high level of EMI shielding. With more sensors in a design and more signals routing across that cable, the job of laying out the board and maximizing reliability becomes more difficult.

Phone Breakdown
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How can designers simplify their board layout, while increasing performance? An option is to use the embedded capabilities in Lattice’s iCE40 family, including the latest addition, iCE40 UltraPlus™ FPGAs, to aggregate signals to the AP. With up to eight DSP blocks and 1 Mb of RAM, these mobile FPGAs are not limited to signal aggregation, but can also process, compute, and store results from sensor data. On-chip DSP resources can increase usage of distributed heterogeneous processing (DHP) to perform repetitive number crunching and minimize the computational overhead on the AP. And the FPGA’s ability to operate on < 35 µA static power helps designers meet the stringent power needs of today’s mobile devices.

What may not be immediately apparent, is how those same FPGAs can be used to simplify board layout. However, by mounting these compact, low power devices next to each sensor, the PCB designer can aggregate multiple signals from the device’s sensors into a simple one- or two-pin differential interface. The fewer the signal lines, the easier it is for the designer to comply with design rules and complete the layout.

Key to achieving this goal are the flexible I/Os on each FPGA. Unlike the fixed I/Os on the AP, the I/Os on each FPGA are reprogrammable. So, if the location of, say, the I3C interface on the AP and the I3C interface on the FPGA don’t align, the designer can simply reprogram the location of the interface on the FPGA to another pin that minimizes routing distance and simplifies board layout.

From the layout engineer’s perspective, this is an ideal solution. You are no longer limited by the fixed pinout of the AP. If you need to move an interface, you simply reprogram it to another location on the FPGA. In doing so, you can not only optimize your board layout, but gain the localized processing resources of the FPGA to distribute processing tasks, accelerate system response time, and improve power efficiency.


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