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Power Management through PMBus and Control PLD

Power Management through PMBus and Control PLD
Posted 02/14/2017 by Shyam Chandra

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In this 6 part series we are looking at the challenges of implementing an efficient power management architecture in today’s complex circuit board designs.

Our previous post covered a hybrid architecture, where the control PLD was splitting the power management responsibilities with a dedicated power manager IC. This next option is used by some designs to replace the dedicated power manager IC with a software driven MCU.

Power Management through PMBus and Control PLD
A Hardware Management System Implemented Using a Control PLD and an MCU

In this architecture, a microcontroller (MCU) manages digitally-controlled point of load (DPOL) supplies using the power management Bus (PMBus) – a two wire communications protocol based on the I²C Bus. As in the power manager IC model, the control PLD remains in control of the board's housekeeping functions, as well as controlling any point-of-load DC-DC converters with an analog control interface (APOLs). To simplify the software design, most MCU-driven power management designs employ time-based sequencing schemes by programming the DPOLs through PMBus. But if a design requires the sequencing combination of both APOL and DPOLs on the board and respond to faults in a uniform manner, the easiest solution would be to let the CPLD control all the supplies on the board using the “Power Good” signals

Pros:

  • Easily scalable designs (for time-based sequencing only).
  • Abundant software development tools make MCU-based solutions faster and easier to debug.
  • Designs can be quickly modified using firmware updates.
  • Reduced routing congestion around DPOLs leads to simpler PCB designs.

Cons:

  • Higher BOM cost.
  • Difficult to scale if event-based sequencing is required.
  • Requires multiple design tools (Verilog/VHDL + software).
  • APOL & DPOL mix requires a hybrid control solution, which has several drawbacks:
    • Difficult to debug when sequencing is partitioned between the DPOL and APOL.
    • APOLs require additional ADC to support telemetry, increasing cost.
    • No hardware simulation support for power management.
    • Hardware management functions testing in prototype board environment only.
    • Increased debug time due to complexity.

This model comes with its own challenges. An MCU is more flexible to program and is easier to debug, but it is much harder to maintain than a dedicated power manager IC. This is because any change to the MCU firmware requires overall system level regression testing. Another potential drawback of this software-based MCU power management is that it is slower to respond to fault conditions (typically 10-15 milliseconds versus the microsecond-scale response of a control PLD). For faster response rates and event-based sequencing, a second layer of protection may need to be added using the control PLD.

Having exhausted the hybrid architectures, our next post will look at an architecture that attempts to supercharge the control PLD with an on-chip digital converter. Read all blogs from our from our Power Manager series:

Click on the links to learn more about our power manager products and development kits and boards.

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