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The Quest for the Optimal Power Management Architecture

The Quest for the Optimal Power Management Architecture
Posted 07/19/2016 by Shyam Chandra

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“Perfection is not attainable, but if we chase perfection we can catch excellence.” – Vince Lombardi

The consumer’s desire for new technology is insatiable. To meet this demand, engineers are constantly striving to make things smaller, faster, cheaper, and better. As sizes shrink and complexity increases, we often find that techniques that have served us well for a long time no longer meet our needs. We must evolve alongside our designs.

Today’s circuit boards (CB) are considerably more complex than previous generations and have started to strain the capabilities of current board-level design methodologies. An area where this can be seen is in the power management architectures. There are already several commonly used methods, however each one comes with trade-offs that are becoming increasingly unpalatable as design complexity increases.

In response, we have developed a new power management architecture that can provide the best performance, safety, and flexibility, while requiring far less design effort and implementation cost. But before we introduce this new power management architecture, we will explore the pros and cons of existing designs in the first installment of this blog series.

Payload vs. Hardware Management

A modern circuit board is typically divided into two functional blocks: payload management and hardware management. In most boards, 80-90% of the CB is dedicated to "payload" functionality (that is the data/control plane elements and/or processors). The remaining 10-20% is reserved for the circuitry, which performs hardware-level monitoring, control, or housekeeping functions including temperature and power management.

Power management (PM) is a critical portion of hardware management since it is responsible for the operation of each power supply within its prescribed limits and its “enable” sequencing during system power-up or power-down. It is also responsible for properly sequencing supplies during fault and reset conditions. The temperature management section ensures that the ICs on the board operate within their allowed temperature range. The remainder of the hardware management section is responsible for performing a variety of housekeeping functions, including system/subsystem reset, JTAG chain management, I2C communications, logic level translation, interface bridging and other board-level control tasks.

Unfortunately, most existing hardware management architectures have difficulty scaling to address the growing complexity of modern payloads, which creates costly challenges. Today, hardware management often consumes a disproportionate share of the overall bill of materials. And while this section typically only occupies 10-20% of the board, its design/debug efforts can consume as much as 30-40% of the overall development time.

Power Management Components

Most power distribution networks employ a hierarchical, or tiered approach, with three distinct classes of DC-DC converters:

  1. Input Supplies convert the board's input supply voltage to the main board rail voltages, which are then used by the board’s other DC-DC converters.
  2. Board Common Supplies generate voltages shared between two or more payload devices (ASIC, SOC, CPU, etc.).
  3. Device Supplies are used exclusively to power individual payload devices.

At the board-level, the power management section must ensure that the ICs operate only when the input power supplies and DC-DC converters used to power the circuit board's payload components are within safe limits. To achieve this, the circuit board power management section should be able to perform the following four classes of critical functions:

  1. Monitoring “Power is Good” – Ensuring that all supply voltages are within safe limits while the board is operating normally. Look for over-voltage and under-voltage faults. When a fault is detected, initiate palliative actions such as activation of “RESET” and “POWER_OK” signals or initiate power down sequencing.
  2. Sequencing Managing Power-On/Power Off – Turning DC-DC converters on or off in a specific order to prevent logical errors or circuit damage.
  3. Sending Control Signals – Generating power-related control signals (Reset, Power OK, etc.) for the payload devices to ensure that the payload devices can begin operation, after the completion of power up sequence, or terminate their operations before initiating power down sequence.
  4. Telemetry or Voltage and Current Value Measurements – During normal operation some boards need to perform voltage measurements of some or all of the DC-DC converters.

The power sequencing will be either Time-Based or Event-Based. In a Time-Based sequencing system, the management circuit turns on supplies in a fixed sequence with pre-defined delays where necessary, to prevent logical errors or damage to ICs. A single fixed sequence of disable signals are used to power down the board when a normal turn-off is requested or when a fault condition is detected. By contrast, Event-Based solutions can provide different responses to different faults. They also can provide fault-dependent power-down sequencing for different levels of faults. Event based sequencing enables a designer to meet modern device supply requirements. In many cases, event based sequencing would be mandatory to prevent damages to large SoCs and FPGAs.

Consequently, designers commonly use arrangements that can implement power management functions using algorithms. One such common arrangement is the use of PLD or control PLD. This control PLD may be a macro cell-based PLD, a CPLD, or a small FPGA.

In our next post, we will look at our first architecture that uses the control PLD for power management functions.

Click on the links to learn more about our power manager products and development kits and boards.

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