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  • Serial Rapid IO 2.1 Endpoint IP Core

    IP Core

    Serial Rapid IO 2.1 Endpoint IP Core

    Compliant with SRIO Rev. 2.1 specification. Up to 3.125Gbps in 1x, 2x and 4x lane configurations. 64-bit internal data paths.
    Serial Rapid IO 2.1 Endpoint IP Core
  • RapidIO 1x LP-Serial Physical Layer Core

    IP Core

    RapidIO 1x LP-Serial Physical Layer Core

    Implements required physical layer (PHY) functionality defined in the RapidIO Physical Layer 1x/4x LP-Serial Specification Revision 1.3
    RapidIO 1x LP-Serial Physical Layer Core
  • Serial RapidIO - Physical Layer Interface

    IP Core

    Serial RapidIO - Physical Layer Interface

    Archived IP Core supporting ORCA FPGAs - For reference only.
     
    Serial RapidIO - Physical Layer Interface
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